The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides techniques for a corner structure to protect an integrated circuit from delamination and cracking during die sawing and packaging. Merely by way of example, the invention has been applied to the manufacture of advanced integrated circuit devices, but it would be recognized that the invention has a much broader range of applicability.
Integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Conventional integrated circuits provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits.
Increasing circuit density has not only improved the complexity and performance of integrated circuits but has also provided lower cost parts to the consumer. An integrated circuit or chip fabrication facility can cost hundreds of millions, or even billions, of U.S. dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of integrated circuits on it. Therefore, by making the individual devices of an integrated circuit smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in integrated fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. Additionally, as devices require faster and faster designs, process limitations exist with certain conventional processes and materials.
For example, manufacturing processes often subject an integrated circuit to mechanical stresses, such as during sawing or packaging. These stresses can cause cracking or delamination. This problem is especially pronounced at interfaces that included materials having significantly different thermal expansion properties, such as between a low k dielectric material and copper.
Accordingly, conventional seal ring techniques have been proposed. These techniques provide a protective barrier around an active region of a chip. Unfortunately, conventional seal ring techniques have certain limitations. For example, a conventional seal ring is generally not sufficiently robust to protect a corner of a chip during the sawing process. A broken corner can initiate many cracks and delamination areas in the conventional seal ring that propagate into an active region of a chip. These and other limitations may be found throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for semiconductor devices is desired.